1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing technologies and more particularly to a hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor).
2. Description of Related Art
A CMOS device integrates both NMOS (N-type Metal Oxide Semiconductor) and PMOS (P-type Metal Oxide Semiconductor) transistors in one device. As the device size continues to shrink, a major challenge in scaling down the channel length is to maintain a high current drive capability (Ion) and a stable threshold voltage, and control the device leakage current (Ioff) at the same time. Short channel effect (SCE) degrades device performance and is a severe obstacle to scale down the channel length.
SOI (Silicon On Insulator) technology uses an ‘engineered’ substrate in place of a conventional bulk silicon substrate. The ‘engineered’ substrate is composed of three layers: a thin monocrystalline silicon top layer with circuits etched thereon; a thin buried oxide (BOX) layer formed of silicon dioxide; and a thick bulk silicon substrate for providing mechanical support to the two layers thereabove. In such a structure, the buried oxide layer separates the monocrystalline silicon top layer from the bulk silicon substrate, so large-area p-n junctions are replaced with a dielectric isolation. Meanwhile, source and drain regions extend downward into the buried oxide layer, which effectively reduce the leakage current and junction capacitance. For nanometer-scale channel length CMOS devices, it is important to control the channel conductance mainly through a gate electric field without being affected by a drain scattering electric field. For SOI devices, the above-described problem is alleviated with the reduced silicon thickness in both partial-depletion and full-depletion structures. Compared with the conventional planar CMOS devices, inversion mode dual-gate or tri-gate fin-type FETs have better gate control and scaling down capabilities. Besides operating in an inversion mode, ultra-thin SOI devices can also operate in an accumulation mode. Comparing to the full-depletion FET, in an accumulation mode, current flows through the whole SOI device, which increases the carrier mobility, reduces low-frequency noises, lowers the short channel effect, and increases the threshold voltage so as to avoid polysilicon gate depletion effect. In an accumulation mode FET, the source and drain regions are doped with impurities of the same type as that in channel region, the charge transfer is of majority carriers, and there is no p-n junction. Since the carrier mobility is the bulk material mobility, the accumulation mode FET achieves high carrier mobility.
Further, in Si(110) substrates, current flows along <110> crystal orientation, hole mobility is more than doubled compared with in conventional Si(100) substrates, and electron mobility is the highest in Si(100) substrates. To fully utilize the advantage of the carrier mobility depending on crystalline orientation, M. Yang et al. at IBM developed a CMOS fabricating technology on hybrid substrates with different crystal orientations (‘High performance CMOS fabricated on hybrid substrate with different crystal orientations’, Digest of Technical Paper of International Electron Devices Meeting, 2003). Through bonding and selective epitaxy growth techniques, an NMOS device is fabricated on a Si (100) surface and a PMOS device is fabricated on a Si (110) surface. The paper reported the drive current of the PMOS device on the Si(110) substrate increases by 45%, when Ioff=100 nA/μm The drawback of this technology is that the PMOS device fabricated in the epitaxial layer is not isolated from the substrate with buried oxide and thus the leakage current will be high.
Therefore, there is a need to develop new CMOSFET devices to overcome the above-described problems.